Keywords: initial, always
There are 2 types of procedural structure statements: initial and always statements. They are the 2 basic statements of behavioral-level modeling.
A module can contain multiple initial and always statements, but these 2 types of statements cannot be nested.
These statements are executed in parallel within the module, regardless of their order in the module.
However, inside an initial or always statement, execution can be understood as sequential (except for non-blocking assignments).
Each initial or always statement generates an independent control flow, and execution time starts from time 0.
initial Statement
The initial statement starts executing at time 0 and executes only once. Multiple initial blocks are independent of each other.
If an initial block contains multiple statements, the keywords begin and end need to be used to form a block statement.
If an initial block contains only one statement, the keywords begin and end may or may not be used.
The initial statement is theoretically non-synthesizable and is mostly used for initialization, signal detection, etc.
Slightly modify the code from the previous section and run a simulation. The code is as follows.
Example
module test ;
reg ai, bi ;
initial begin
ai = 0 ;
#25 ; ai = 1 ;
#35 ; ai = 0 ; //absolute 60ns
#40 ; ai = 1 ; //absolute 100ns
#10 ; ai = 0 ; //absolute 110ns
end
initial begin
bi = 1 ;
#70 ; bi = 0 ; //absolute 70ns
#20 ; bi = 1 ; //absolute 90ns
end
//at proper time stop the simulation
initial begin
forever begin
#100;
//$display("---gyc---%d", $time);
if ($time >= 1000) begin
$finish ;
end
end
end
endmodule
The simulation results are as follows:
It can be seen that when the 2 initial process statements assign values to signals ai and bi respectively, they do not affect each other.
The values of signals ai and bi change sequentially according to the assignment order, so the statements inside initial can also be regarded as sequential execution.
always Statement
Unlike the initial statement, the always statement is executed repeatedly. The always statement block starts executing its behavioral statements from time 0; after executing the last statement, it executes the first statement in the block again, repeating this cycle.
Due to its cyclic execution feature, the always statement is often used for generating simulation clocks, detecting signal behavior, etc.
Below, the always statement is used to generate a 100MHz clock source, and the simulation is stopped at 1010ns. The code is as follows.
The code is as follows:
Example
module test ;
parameter CLK_FREQ = 100 ; //100MHz
parameter CLK_CYCLE = 1e9 / (CLK_FREQ * 1e6) ; //switch to ns
reg clk ;
initial clk = 1'b0 ; //clk is initialized to "0"
always # (CLK_CYCLE/2) clk = ~clk ; //generating a real clock by reversing
always begin
#10;
if ($time >= 1000) begin
$finish ;
end
end
endmodule
The simulation results are as follows:
It can be seen that the clock period is the desired 100MHz. Moreover, the simulation stops at 1010ns.
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