Format

Verilog is case-sensitive.

The format is free; it can be written on a single line or across multiple lines.

Each statement must end with a semicolon. Whitespace (newlines, tabs, spaces) has no actual meaning and can be ignored during compilation. For example, the following two programming styles are equivalent.

No line breaks (not recommended)

Example

wire [1:0]  results ;assign results = (a == 1'b0) ? 2'b01 ： (b==1'b0) ? 2'b10 ： 2'b11 ;

Line breaks (recommended)

Example

wire [1:0]  results ;
assign      results = (a == 1'b0) ? 2'b01 ：
            (b==1'b0) ? 2'b10 ：
                2'b11 ;

Comments

There are 2 ways to write comments in Verilog:

use//For single-line comments:

reg [3:0] counter ;  // A definition of counter register
use/*and*/For multi-line comments:
wire [11:0]  addr ;
/* 
Next are notes with multiple lines.
Codes here cannot be compiled.
*/
assign   addr = 12'b0 ;

Identifiers and Keywords

An identifier can be any set of letters, digits,$symbols, and_a combination of (underscore) symbols.

Additionally, identifiers are case-sensitive.

Keywords are special identifiers reserved in Verilog for defining language constructs.

All keywords in Verilog are lowercase.

Example

reg [3:0] counter ; //reg is a keyword, counter is an identifier
input clk; //input is a keyword, clk is an identifier
input CLK; //CLK and clk are 2 different identifiers