Keywords: specify, path delay
Path delays are described using the keywords specify and endspecify, which form a specify block statement.
specify is an independent part of a module and cannot appear in other statement blocks (initial, always, etc.).
The specify block statement mainly has the following functions:
- Specify pin-to-pin delays on all paths;
- Define specparam constants;
- Set up timing checks in the circuit.
Parallel connection
Each path has a source pin and a destination pin. Describing the delays of these paths one by one with specify statements is called a parallel connection.
The format for parallel connection usage is as follows:
(<source_io> => <destination_io>) = <delay_value> ;
A 4-input AND logic module model with path delays is described as follows:
Example
output out,
input a, b, c, d);
specify
(a => out) = 2.5 ;
(b => out) = 2.5 ;
(c => out) = 3.5 ;
(d => out) = 3.5 ;
endspecify
wire an1, an2 ;
and (an1, a, b);
and (an2, c, d);
and (out, an1, an2);
endmodule
The keyword specparam can be used in a specify block to define delay value constants, which are then assigned to path delays.
Constants defined by specparam can only be used inside the specify block.
Example
specparam ab_2_out = 2.5 ;
specparam cd_2_out = 3.5 ;
(a => out) = ab_2_out ;
(b => out) = ab_2_out ;
(c => out) = cd_2_out ;
(d => out) = cd_2_out ;
endspecify
In a parallel connection, source pins and destination pins correspond one-to-one. Parallel connections also support path delay descriptions between multi-bit signals, but the bit widths must be consistent.
Example
input [3:0] d,
output [3:0] q);
specify
(d => q) = 3 ;
endspecify
assign q = d & 0101 ;
endmodule
Here, the specify block statement can also be written in expanded form; the two expressions are equivalent.
Example
(d[0] => q[0]) = 3 ;
(d[1] => q[1]) = 3 ;
(d[2] => q[2]) = 3 ;
(d[3] => q[3]) = 3 ;
endspecify
Full connection
In a full connection, every bit of the source pin is connected to every bit of the destination pin.
The connections between source pins and destination pins are combinatorially traversed, and bit width correspondence is not required.
The format for full connection usage is as follows:
(<multiple_source_io> *> <multiple_destination_io>) = <delay_value> ;
For example, a 4-input AND logic module can be described as follows:
Example
output out,
input a, b, c, d);
specify
(a,b *> out) = 2.5 ;
(c,d *> out) = 3.5 ;
endspecify
wire an1, an2 ;
and (an1, a, b);
and (an2, c, d);
and (out, an1, an2);
endmodule
Edge-sensitive path
Edge-sensitive paths are used for timing modeling of input-to-output delays and use edge identifiers to specify trigger conditions. If not specified, any change will trigger a change in the delay value from the source pin to the destination pin.
Usage examples are as follows:
Example
//The data path from in to out is non-inverting, i.e., out = in
(posedge clk => (out +: in)) = (1,2);
//On the falling edge of clk, the rise delay from clk to out is 1, and the fall delay is 2
//The data path from in to out is inverting, i.e., out = ~in
(negedge clk => (out -: in)) = (1,2);
//When clk changes arbitrarily, the rise delay from clk to out is 1, and the fall delay is 2
//The data path from in to out is unpredictable; non-inverting, inverting, or unchanged
(negedge clk => (out : in)) = (1,2);
Conditional path
Verilog also allows different conditional assignments to path delays in a model based on different signal values.
Operands in conditions can be scalars or vectors, and conditional expressions can contain any operators.
Note that only if statements should be used to fully declare all input states in conditional paths. Undeclared paths will use distributed delays; if distributed delays are also not declared, zero delays will be used. If both path delays and distributed delays are declared, the largest delay will be selected as the path delay.
However, if statements in specify cannot use the else construct; ifnone can be used to describe path delays for the default condition.
Example
if (a) (a => out) = 2.5 ;
if (~a) (a => out) = 1.5 ;
if (b & c) (b => out) = 2.5 ;
if (!(b & c)) (b => out) = 1.5 ;
if ({c, d} == 2'b01)
(c,d *> out) = 3.5 ;
ifnone (c,d *> out) = 3 ;
endspecify
Gate delay path
Gate delays (rise delay, fall delay, turn-off delay) can also be described using the path delay method.
The number of delay paths that can be defined is 1, 2, 3, 6, or 12; other numbers of delay values are incorrect.
The following examples illustrate how path delays are expressed in gate delay models.
Example
specify
specparam t_delay = 1.5 ;
(clk => q) = t_delay ;
endspecify
//2 parameters: rise delay (0->1, z->1, 0->z) = 1.5
// fall delay (1->0, z->0, 1->z) = 2
specify
specparam t_rise = 1.5, t_fall = 2 ;
(clk => q) = (t_rise, t_fall) ;
endspecify
//3 parameters: rise delay (0->1, z->1) = 1.5
// fall delay (1->0, z->0) = 2
// turn-off delay (1->z, 0->z) = 1.8
specify
specparam t_rise = 1.5, t_fall = 2, t_turnoff = 1.8 ;
(clk => q) = (t_rise, t_fall, t_turnoff);
endspecify
//6 parameters: corresponding to 0->1, 1->0, 0->z, z->1, 1->z, z->0 respectively
specify
specparam t_01 = 1.5, t_10 = 2, t_0z = 1.8 ;
specparam t_z1 = 2, t_1z = 2.2, t_z0 = 2.1 ;
(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0) ;
endspecify
//12 parameters: corresponding to 0->1, 1->0, 0->z, z->1, 1->z, z->0 respectively
// 0->x, x->1, 1->x, x->0, x->z, z->x
specify
specparam t_01 = 1.5, t_10 = 2, t_0z = 1.8 ;
specparam t_z1 = 2, t_1z = 2.2, t_z0 = 2.1 ;
specparam t_0x = 1.1, t_x1 = 1.2, t_1x = 2.1 ;
specparam t_x0 = 2, t_xz = 2 , t_zx = 2.1 ;
(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0,
t_0x, t_x1, t_1x, t_x0, t_xz, t_zx) ;
endspecify
In gate path delay models, maximum, minimum, and typical values can also be specified.
Example
specify
specparam t_rise = 1:1.5:1.8;
specparam t_fall = 1:1.8:2 ;
specparam t_turnoff = 1.1:1.2:1.3 ;
(clk => q) = (t_rise, t_fall, t_turnoff);
endspecify
X transmission delay
If the delay for x transition time is not specified (12 delay parameters are not given in the gate path delay), the following rules apply:
- The delay time for transitioning from x to a known state is the maximum delay time that may be required;
- The delay time for transitioning from a known state to x is the minimum delay time that may be required.
For example, when 6 delay parameters are given in the gate path delay, the x transmission delay times are defined as shown in the following table:
| x transition | Delay value |
|---|---|
| 0->x | min(t_01, t_0z) |
| 1->x | min(t_10, t_1z) |
| z->x | min(t_z1, t_z0) |
| x->0 | max(t_10, t_z0) |
| x->1 | max(t_01, t_z1) |
| x->z | max(t_1z, t_0z) |
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