Verilog is mainly used for describing digital circuit designs, but not all descriptive methods can be synthesized into actual hardware circuits. For example, some keywords used for simulation verification belong to the simulation verification language and can only be used during simulation; they cannot be synthesized into circuits, such as system tasks $dsiplay, initial statements, etc. Therefore, when using Verilog to design digital circuits, special attention must be paid to circuit synthesizability. Testbenches can be written as freely as desired, as long as the required simulation stimulus conditions can be constructed.
Synthesizable and Non-Synthesizable Structures
Structures supported by all synthesis tools
| Structure Type | Keyword | Description |
|---|---|---|
| Port signals | inout，input，output | There are only 3 types of port signals |
| Parameter | parameter, localparam | --- |
| Signal variables | wire, reg, tri, integer | --- |
| Module | module | --- |
| Gate-level primitives | and，nand，or，nor，xor，xnor，buf，not，bufif0，bufif1，notif0，notif1，supply0，supply1 | Just instantiate them directly |
| Instantiation | --- | Supports module instantiation, gate-level primitive instantiation, etc. |
| Functions and tasks | function, task | Supports descriptions without timing structures |
| Continuous assignment | assign | Does not support descriptions with delays |
| Procedural assignment | always, begin, end | Can design sequential logic or combinational logic |
| Conditional statements | if, case, default | Conditions cannot include comparisons with 'z' or 'x' |
| Loop statements | for, while, forever | while and forever must contain @(posedge clk) or @(negedge clk) to avoid combinational logic loops |
| Edge-triggered | negedge，posedge | --- |
| Operators | --- | Supports all operators except '===' and '!==' |
Structures not supported by any synthesis tool
| Structure Type | Keyword | Description |
|---|---|---|
| Variable types | time | Time-type variables used during simulation |
| System tasks | --- | Most system tasks assist simulation and cannot be synthesized into actual circuits For example, $display, $fopen, $finish, etc. |
| Procedural structures | initial | initial is commonly used to assign initial values to signals during simulation or to control the timing of stimulus signals |
| Parallel statements | fork, join | Commonly used to describe parallel structures in simulation Parallel structures described by always @(posedge clk) are synthesizable |
| Delay statements | # | All descriptions with the delay symbol '#' are non-synthesizable However, circuits will have delays during simulation, and synthesis will not report errors |
| Level-sensitive triggering | wait | Mainly used for signal detection and initiation in simulation |
| Force assignment and release | force, release | Mainly used in simulation to block other driving sources and force-assign signals |
Structures that synthesis tools may support
| Structure Type | Keyword | Description |
|---|---|---|
| x/z conditional statements | casex, casez | Some synthesis tools can recognize the non-'x/z' comparison logic in these statements |
| Nets of different strengths | wand，triand，wor，trior | Needed when a signal has multiple driving sources But digital design has now largely abandoned these variable types |
| Real variables | real | Often used for precise calculations in simulation |
| Process termination | disable | Terminates execution of a procedural block; most synthesis tools do not support this command |
| Loop statements | repeat, while, forever | repeat is commonly used in simulation to execute statements a fixed number of times while and forever may also be synthesizable when the loop count is a constant |
| User-defined primitives (UDP) | UDP | In fact, most synthesis tools currently support UDP It's just that some older synthesis tools do not recognize it |
| Procedural continuous assignment | assign, deassign | Most tools do not support synthesis of the reg data type under this operation They support synthesis of the wire data type under this operation |
Synthesizable Design Recommendations
When using Verilog for digital design, the following principles should be followed: synthesizable structures can be used boldly, non-synthesizable structures are used in simulation, and structures supported by some synthesis tools but not others should be avoided as much as possible.
Unless in certain special designs, such as clock gating, clock switching circuits, etc., do not write logic in the design that could potentially be synthesized into a latch. SeeVerilog Tutorial, Section "6.5 Verilog Avoiding Latches"。
When declaring variables, do not follow the C language format of assigning initial values to register variables. During simulation, variables will have the configured initial values, but after synthesis, the initial register values are indeterminate. If the initial signal values affect the logic function, the simulation process may miss opportunities to identify logic errors due to insufficient verification.
All internal registers should have initial values assigned via reset, to ensure every register has a stable state when the system is reset. Without a reset pin, the initial values of registers in the synthesized circuit cannot be determined, which may lead to functional errors.
Use blocking assignments for combinational logic and non-blocking assignments for sequential logic. Combinational logic is generally described with the continuous assignment statement assign. Circuits described with always can also be synthesized as combinational logic. For example, an "AND logic" can be described as follows:
always @（*） begin
F = A & B ;
end
Signals assigned in an always statement must be declared as reg type. In combinational logic, this reg variable will be synthesized into a wire net; in sequential logic, this reg variable will be synthesized into a flip-flop.
The same variable cannot be controlled by multiple clocks (or always blocks), nor can it be controlled by both edges of a clock. Such descriptions are also non-synthesizable.
Avoid xXorZvalues in the design, because synthesis tools can only recognize 0/10or1logic values.